During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board that are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.
While the above-described testing environment works well in many applications, it is not without its limitations and disadvantages. For example, it is very difficult to test various timing characteristics of the integrated circuits, particularly at the high operating speeds for which such integrated circuits are designed. This difficulty in testing timing characteristics results primarily from the propagation delays in the cable coupling the tester to the test head. The cables that are typically used in such testing environments are often fairly long, thus making the delays of signals coupled to and from the integrated circuits correspondingly long and often difficult to predict.
Another problem with the above-described testing environment is that it may not accurately simulate the conditions in which the integrated circuits will be actually used. In actual use, integrated circuits, such as dynamic random access memory (“DRAM”) devices are typically mounted on a printed circuit board. Signals are applied to the integrated circuits by other integrated circuits mounted on the board, and signals generated by the integrated circuits are received by other integrated circuits mounted on the board. In most applications, signals are not coupled to and from the integrated circuits through long cables coupled to distant electronic devices. Therefore, the testing environment is normally quite different from the environment in which the integrated circuits will operate in normal use.
While techniques have been developed to deal with these difficulties, the use of these techniques results in testers that are highly complex and often very expensive. A large number of testers are normally required for a high capacity semiconductor fabrication plant, thus greatly increasing the cost of the plant and the expense of testing the integrated circuits.
One improved testing system that has been proposed is to fabricate an integrated test circuit that performs most if not all of the functions of conventional testers, and mount the integrated test circuit on the test head or load board to which the integrated circuits being tested are coupled. By placing the testing function on the test head or load board itself, the problems inherent in coupling test signals between a testing system and a test head are eliminated. As a result, the circuits can be tested in a more realistic environment. Furthermore, since even custom integrated circuits can be fabricated relatively inexpensively, the cost of testing systems can be greatly reduced.
One difficulty in using an integrated test circuit in this manner stems from the difficulty in accurately testing timing margins of integrated circuits, such as memory devices. For example, two memory device timing parameters that are normally tested are the maximum data set-up time, which is abbreviated as tDQSQ, and the minimum data hold time, which is abbreviated as tQH. In source synchronous data transfers, read data signals DQ are transmitted in synchronism with a data strobe signal DQS. With reference to FIG. 1, the data strobe signal DQS transitions active at time t0, and the read data signals DQ thereafter become valid. The maximum time needed for the read data signals DQ to become valid after the transition of DQS at t0, i.e., the data set up time tDQSQ, is normally specified for a memory device. Similarly, the minimum time that the read data signals DQ must remain valid after the transition of DQS at t0, i.e., the data hold time tQH, is also normally specified for a memory device.
The time between tDQSQ and tQH is the data valid period. The length of the data valid period may be excessively reduced by any increase in the set-up time beyond the specified maximum set-up time tDQSQ or any decrease of the data hold time from the specified minimum data hold time tQH. A device receiving the data bits DQ and data strobe DQS signal, such as a memory controller, normally attempts to delay the DQS signal so that it transitions at the center of the data valid period. As the length of the data hold period gets smaller, it becomes more difficult for the memory device to position transitions of the DQS signal in the data valid period. It is therefore important to determine the data set-up and data hold times of a memory device being tested to ensure that a sufficient data valid period can be achieved.
Unfortunately, with modern high-speed memory devices, it is difficult to measure very small time periods, such as tDQSQ and tQH, that must be measured to adequately test memory devices. Expensive high-speed testers of the type described above are capable of measuring these very small time periods. However, the lack of a good timing mechanism that can easily be fabricated in an integrated circuit threatens to preclude the use of an integrated test circuit mounted on a load board or test head from accurately testing tDQSQ and tQH.
There is therefore a need for a testing system and method that can be easily fabricated in an integrated circuit to allow an integrated test circuit mounted on a load board, test head or the like to accurately measure very small timing margins, such as tDQSQ and tQH.